ST/개발 환경 및 구조

CMSIS

engineer4ever 2025. 3. 18. 00:03

 

CMSIS(Common Microcontroller Software Interface Standard)는 Arm Cortex 프로세서를 기반으로 하는 마이크로 컨트롤러용 벤더 독립 추상화 레이어.CMSIS는 범용 툴인터페이스를 정의하고 일관된 디바이스 지원 가능. CMSIS 소프트웨어 인터페이스는 소프트웨어 재사용을 단순화하고 마이크로컨트롤러 개발자의 학습 곡선을 줄이며 새로운 기기의 시장 출시 기간을 단축.

 

CMSIS는 프로세서 및 주변기기, 실시간 운영체제 및 미들웨어 컴포넌트에 대한 인터페이스를 제공. CMSIS에는 디바이스, 보드 및 소프트웨어의 전송 메커니즘이 포함되어 있어 여러 벤더의 소프트웨어 컴포넌트를 조합 가능.

 

https://www.keil.arm.com/cmsis

 

Arm Keil

Keil MDK, Keil Studio Cloud and Keil Studio for VS Code. As flexible as you are: from cloud to desktop, from CLI to GUI, running on macOS, Linux, and Windows

www.keil.arm.com

 

CMSIS
Target Processors
Description
Core(M)
All Cortex-M, SecurCore
Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.
Core(A)
Cortex-A5/A7/A9
Standardized API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.
Driver
All Cortex
Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.
DSP
All Cortex-M
DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.
NN
All Cortex-M
Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.
RTOS v1
Cortex-M0/M0+/M3/M4/M7
Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.
RTOS v2
All Cortex-M, Cortex-A5/A7/A9
Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface.
Pack
All Cortex-M, SecurCore, Cortex-A5/A7/A9
Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software reuse and product life-cycle management (PLM).
SVD
All Cortex-M, SecurCore
Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.
DAP
All Cortex
Firmware for a debug unit that interfaces to the CoreSight Debug Access Port.
Zone
All Cortex-M
Defines methods to describe system resources and to partition these resources into multiple projects and execution areas.

 

 

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