STM32F103x Core registers

 

PM0056 : STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 programming manual p.14

 

1. General-purpose registers

R0-R12은 32-bit general-purpose registers for data operations.

 

2. SP(Stack pointer)

The SP is register R13. In Thread mode, bit[1] of the CONTROL register

indicates the stack pointer to use:

• 0 = Main Stack Pointer (MSP). This is the reset value.

• 1 = Process Stack Pointer (PSP).

On reset, the processor loads the MSP with the value from address 0x00000000.

 

3. LR(Link register)

The LR is register R14. It stores the return information for subroutines,

function calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF.

 

4. PC(Program counter)

The PC is register R15. It contains the current program address. Bit[0] is

always 0 because instruction fetches must be halfword aligned. On reset, the processor

loads the PC with the value of the reset vector, which is at address 0x00000004.

 

5. PSR(Program status register)

The PSR combines:

• Application Program Status Register (APSR)

• Interrupt Program Status Register (IPSR)

• Execution Program Status Register (EPSR)

 

6. APSR(Application program status register)

The APSR contains the current state of the condition flags from previous instruction

executions. See the register summary in Table 2 on page 15 for its attributes. The bit

assignments are:

 

7. IPSR(Interrupt program status register)

The IPSR contains the exception type number of the current Interrupt Service Routine

(ISR).

 

8. EPSR(Execution program status register)

The EPSR contains the Thumb state bit, and the execution state bits for either the:

• If-Then (IT) instruction

• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store

multiple instruction.

 

9. Interruptible-continuable instructions

When an interrupt occurs during the execution of an LDM or STM instruction, the processor:

• Stops the load multiple or store multiple instruction operation temporarily

• Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

• Returns to the register pointed to by bits[15:12]

• Resumes execution of the multiple load or store instruction.

When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.

 

10. If-Then block

The If-Then block contains up to four instructions following a 16-bit IT instruction. Each

instruction in the block is conditional. The conditions for the instructions are either all the

same, or some can be the inverse of others. See IT on page 94 for more information.

 

11. Exception mask registers

The exception mask registers disable the handling of exceptions by the processor. Disable

exceptions where they might impact on timing critical tasks.

 

12. Priority mask register

The PRIMASK register prevents activation of all exceptions with configurable priority.

 

13. Fault mask register

The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).

 

14. BASEPRI(Base priority mask register)

The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value.

 

15. CONTROL register

The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode.

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그러면 도대체 이걸 왜 알아야 할까?

 

1. 시스템 초기화 및 설정

- RESET 및 초기화 과정

시스템이 리셋되었을 때 코어 레지스터를 통해 프로세서 상태를 파악하거나 기본 설정을 진행

 

- 시작 코드 작성

코어 레지스터를 활용해 초기 스택 포인터, 인터럽트 벡터 위치 등을 설정

 

2. 인터럽트 및 예외 처리

- 인터럽트 우선순위 관리

Nested Vectored Interrupt Controller(NVIC) 관련 코어 레지스터를 사용해 우선순위를 설정하거나 특정 인터럽트를 활성화/비활성화

 

- 예외 처리 분석

Fault 상태 레지스터(CFSR, HFSR 등)를 통해 오류의 원인을 분석하고 적절히 대처

 

3. 디버깅 및 시스템 동작 확인

- 실행 상태 확인

Program Counter(PC), Link Register(LR), Stack Pointer(SP)를 통해 현재 실행 중인 명령어 위치, 함수 복귀 주소, 스택 상태를 확인

 

- 오류 원인 추적

Hard Fault나 Usage Fault 발생 시 Fault 관련 레지스터를 읽어 문제 발생 위치와 원인을 파악

 

4. 시스템 동작 최적화

- 전력 관리

Sleep 모드 설정(SCR) 또는 저전력 대기 상태 진입 시 사용

예: SLEEPONEXIT 비트를 설정하여 특정 조건에서 자동으로 Sleep 상태로 전환

 

- RTOS와의 연동

Process Stack Pointer(PSP)와 Main Stack Pointer(MSP)를 스위칭하여 태스크 간 전환을 효율적으로 관리

 

5. 주기적 동작 관리

- SysTick Timer 활용

SysTick 레지스터를 통해 주기적인 인터럽트를 생성하여 OS Tick 또는 타이머 이벤트를 구현

 

6. 사용자 코드 보호

- FAULTMASK, PRIMASK

중요 코드 실행 중 인터럽트를 제한하거나, 특정 크리티컬 섹션 보호를 위해 인터럽트를 마스킹